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CS Energy
Results: 537

#	Item
311	Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing∗ Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:24:42 Integrated circuits Dynamic voltage scaling Energy conservation IC power supply pin Operational amplifier Threshold voltage Subthreshold conduction Digital electronics Voltage and frequency scaling Electronic engineering Electrical engineering Electronics
312	Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules ∗ Aditya Agrawal, Amin Ansari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma. Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-01-14 22:55:13 Computing EDRAM Memory refresh Dynamic random-access memory CPU cache Bloom filter Tile Cache Computer memory Computer hardware Visual arts
313	Microsoft PowerPoint - present_micro00 [Compatibility Mode] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-30 23:33:48 Computing Central processing unit Thermodynamics Dynamic random-access memory Dynamic voltage scaling CPU cache Temperature Computer hardware Computer memory Energy conservation
314	PDF Document Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-03-29 16:26:46
315	Profile-Based Energy Reduction for High-Performance Processors Michael Huang, Jose Renau, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-12-10 19:52:52 Computer architecture Profilers Software optimization CPU cache Cache Computer memory Profiling Program optimization Microarchitecture Computing Computer hardware Central processing unit
316	Positional Adaptation of Processors: Application to Energy Reduction ∗ Michael C. Huang Jose Renau and Josep Torrellas Dept. of Electrical and Computer Engineering Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-04-01 22:17:30 Subroutines Cache Holism Source code University of Cambridge Computer Laboratory Call stack CPU cache Parameter Algorithm Software engineering Computing Computer programming
317	L1 Data Cache Decomposition for Energy Efficiency Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 11:58:14 Cache CPU cache Computer architecture Computing R10000 Computer hardware Central processing unit Computer memory
318	Extreme Scale Computer Architecture: Energy Efficiency from the Ground Up Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-06-21 19:03:22 Voltage regulator Multi-core processor Electronics Electronic engineering Electromagnetism
319	Contents Editor ： Hisao Makino (Dr.) Director Consulting & Solution Team CS Promotion Division Central CS Promotion Office Hiromitsu Matsuda Senior Research Scientist Add to Reading List Source URL: criepi.denken.or.jp Language: English - Date: 2009-12-25 03:51:56 Matter Bituminous coal Anthracite Lignite Sub-bituminous coal Fly ash Fossil-fuel power station Fossil fuel Coal assay Coal Energy Chemistry
320	Energy Efficient Hybrid Wakeup Logic Michael Huang, Jose Renau, and Josep Torrellas University of Rochester, University of Illinois at Urbana-Champaign* Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-29 12:05:14 Science Academia Knowledge Digital electronics Register file Logic

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